[
    {
        "PEBS": "1",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.",
        "Counter": "32",
        "UMask": "0x1",
        "PEBScounters": "32",
        "EventName": "INST_RETIRED.ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of instructions retired. (Fixed event)"
    },
    {
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.",
        "Counter": "33",
        "UMask": "0x2",
        "PEBScounters": "33",
        "EventName": "CPU_CLK_UNHALTED.CORE",
        "PDIR_COUNTER": "na",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)"
    },
    {
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  The core frequency may change from time.  This event is not affected by core frequency changes and at a fixed frequency.  This event uses fixed counter 2.",
        "Counter": "34",
        "UMask": "0x3",
        "PEBScounters": "34",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "PDIR_COUNTER": "na",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)"
    },
    {
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses a programmable general purpose performance counter.",
        "EventCode": "0x3c",
        "Counter": "0,1,2,3",
        "PEBScounters": "0,1,2,3",
        "EventName": "CPU_CLK_UNHALTED.CORE_P",
        "PDIR_COUNTER": "na",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of unhalted core clock cycles."
    },
    {
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts reference cycles (at TSC frequency) when core is not halted.  This event uses a programmable general purpose perfmon counter.",
        "EventCode": "0x3c",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "PEBScounters": "0,1,2,3",
        "EventName": "CPU_CLK_UNHALTED.REF",
        "PDIR_COUNTER": "na",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency."
    },
    {
        "PEBS": "1",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.",
        "EventCode": "0xc0",
        "Counter": "0,1,2,3",
        "PEBScounters": "0,1,2,3",
        "EventName": "INST_RETIRED.ANY_P",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of instructions retired."
    },
    {
        "CollectPEBSRecord": "2",
        "EventCode": "0xc3",
        "Counter": "0,1,2,3",
        "PEBScounters": "0,1,2,3",
        "EventName": "MACHINE_CLEARS.ANY",
        "PDIR_COUNTER": "na",
        "SampleAfterValue": "20003",
        "BriefDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist."
    },
    {
        "PEBS": "1",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.",
        "EventCode": "0xc4",
        "Counter": "0,1,2,3",
        "PEBScounters": "0,1,2,3",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Counts the number of branch instructions retired for all branch types."
    },
    {
        "PEBS": "1",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.",
        "EventCode": "0xc5",
        "Counter": "0,1,2,3",
        "PEBScounters": "0,1,2,3",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Counts the number of mispredicted branch instructions retired."
    },
    {
        "CollectPEBSRecord": "2",
        "EventCode": "0xcd",
        "Counter": "0,1,2,3",
        "PEBScounters": "0,1,2,3",
        "EventName": "CYCLES_DIV_BUSY.ANY",
        "PDIR_COUNTER": "na",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts cycles the floating point divider or integer divider or both are busy.  Does not imply a stall waiting for either divider."
    }
]